1. Field of the Invention
The present invention relates to a precharging circuit fabricated in an IC (integrated circuit) chip or die, and, more particularly, to such a precharging circuit which may be fabricated using conventional MIST devices and which is small in size, yet affords a long charging time interval.
2. State of the Prior Art
A precharging circuit having an extremely large time constant charging characteristic often is required in IC devices. A typical example of the use of such a circuit is for generating an E-W (erasing and writing) voltage, which has a characteristic that it gradually rises in voltage over a long time interval from a low level to a high level, for example, 20-30 volts, in contrast to the ordinary power supply voltage of 5 volts for IC devices. The E-W voltage is used for changing the data stored in an EEPROM (electrically erasable programmable read only memory) or a NOVRAM (nonvolatile random access memory), such as may be fabricated in a common memory chip with the precharging circuit. Typically, the E-W voltage is generated in response to a change command applied to the memory chip from a computer system in which the memory chip is incorporated.
The NOVRAM combines the functions of a static RAM (SRAM) and an EEPROM, so that it operates as a SRAM when the computer system is operating; however, the data in the SRAM is transferred to the EEPROM and stored therein when the power supply for the computer system is turned off. Since the NOVRAM is a special type of EEPROM and since the precharging circuit of the present invention is equally applicable thereto, for convenience, further reference herein shall be limited solely to EEPROM devices, it being understood that such reference encompasses NOVRAM and other similar such devices.
EEPROM devices are used extensively in computer systems, because the data stored therein can easily be changed, particularly by comparison with other EPROM (erasable programmable read only memory) devices. For example, whereas UV-EPROM (ultraviolet rays-controlled EPROM) devices as well have been employed extensively in computer systems, they present certain inconveniences. Particularly, a UV-EPROM memory chip, or a board on which such a memory chip is mounted, must be removed from the computer system to permit irradiating same with ultraviolet rays for erasing the data stored therein when the data must be changed. By contrast, in an EEPROM device, the data can easily be changed electrically, by a program previously provided for that purpose, thus eliminating any need to remove the associated memory chip, or a board on which the chip is mounted, from the computer system.
EEPROM devices, however, present a different problem, namely that the E-W voltage must be applied to the EEPROM for a lengthy time interval, in the range of from 100 micro-sec (.mu.S) to 10 mill-sec (mS), for changing the data therein. Such a time interval is extraordinarily great, particularly in the context of the nanosecond speeds of operation common in the computer field today. Thus, it is difficult to provide such a long time interval, in a computer system. Moreover, the means for establishing the requisite time interval of the E-W voltage usually are provided in a memory chip; absent that provision, for example, if means external to the chip are employed, the processing speed of the computer system almost invariably will be reduced. As a specific example, if the CPU (central processing unit) of the computer system is employed for this purpose, it would be occupied for an extensive period in generating the lengthy time interval of the E-W voltage for changing the data in the EEPROM, with the result that the overall processing speed of the computer system necessarily would be significantly decreased. Conversely, if the time interval determining means is provided directly on the memory chip, the problem is pressented that a significant amount of space on the chip is required therefor, contributing to increased fabricating costs for the chip.
When an E-W voltage having the described, requisite waveform is applied to the EEPROM, electrons or holes are injected into the EEPROM, functioning in accordance with the well known tunneling phenomenon, for erasing or writing data therein; however, if the E-W voltage were to increase rapidly to the high level, the tunnel effect layer fabricated within the EEPROM would break down. Thus, it is critical that the E-W voltage waveform have a gradually rising leading edge, to achieve accurate operations. Consistent therewith, the E-W voltage for an EEPROM typically must have a waveform which rises gradually from a low to a high level over a lengthy time interval, such as from 100 .mu.S to 500 .mu.S, and then remains at the high level for an extremely long time interval, such as from 5 mS to 10 mS, both for erasing the stored data and for writing new data into the EEPROM.
Typically, a high voltage waveform generator is employed to generate the E-W voltage of the requisite waveform including the gradual leading or rising edge, and a timer circuit controls the long time interval, as is required for erasing and writing operations. Both the waveform generator and the timer circuit are fabricated in the IC chip and have respectively associated therewith a precharging circuit. The typical precharging circuit comprises, essentially, an RC (resistor and capacitor) circuit having a long time constant; moreover, in the timer circuit, the long time interval is determined by the time period from the initiation of the precharging operation to the completion thereof, at which the voltage level of the precharging node (i.e., a circuit node at which the requisite precharging voltage is developed) reaches a predetermined value. A high voltage source establishes the predetermined value for the precharging operation, in order to prolong the time interval.
FIG. 1(a) is a circuit schematic of a prior art precharging circuit. A depletion (D)-type MIST (metal insulator semiconductor transistor) T.sub.R functions as the resistor (R) of the RC time constant charging circuit, and is connected between a high voltage source V.sub.pp and a capacitor C. A charging current flows from the high voltage source V.sub.pp through transistor T.sub.R to the capacitor C, producing a precharging voltage V.sub.n at the circuit node, or connection, between transistor T.sub.R and capacitor C, which voltage V.sub.n increases with time, as shown in FIG. 1(b). In particular, the precharging voltage V.sub.n increases from essentially zero volts (0 V) to a value slightly less than that of the high voltage source V.sub.pp over the time interval t=0 to t=t.sub.4. The voltage V.sub.n thereafter asymptotically approaches that of the high voltage source V.sub.pp, over the time interval t=t.sub.4 to t=t.sub.5. For purposes of erasing data stored in an EEPROM, the time interval t=0 to t=t.sub.4 is approximately from 100 .mu.S to 500 .mu.S; for the case of writing new data into an EEPROM, the time interval t=0 to t=t.sub.5 is 5 mS to 10 mS. The specific time intervals employed for the respective erasing and writing operations, within the indicated ranges, are dependent upon the characteristics of the particular EEPROM.
As before noted, a precharging circuit as shown in FIG. 1(a) may be associated with each of a high voltage waveform generator and a timer circuit, which respectively function as hereinbefore set forth. Each of the high voltage waveform generator and the timer circuit are triggered by the E-W control signals applied externally to the EEPROM chip by the computer system. Typically, a high voltage in the range of 25 V (volts) is required for generating the long time interval in the RC circuit, and typically is supplied from a high voltage source fabricated in the IC chip. Particularly, the high voltage source comprises a clock oscillator and a charge-pumping circuit, the clock oscillator generating a clocking signal, or train, comprising series of clock pulses, the charge-pumping circuit functioning under the control of the clock pulses to produce the requisite high voltage.
Prior art precharging circuits of the type shown in FIG. 1(a) however, present problems as to the fabrication of the capacitor C and the transistor T.sub.R, with associated operational problems. Particularly, capacitor C must have a quite large value of capacitance, such as greater than 10 picofarad (pF) for obtaining a sufficiently long time constant, such as in the range of from 10 .mu.S to 10 mS; further, since the dielectric material of the capacitor C is afforded by an insulating layer (typically silicon dioxide), the layer must be of substantial thickness so as to withstand the high voltage to be developed. As a result, the capacitor must be of substantial size, for example, from a minimum of 100.times.100 .mu.m.sup.2 to 400.times.400 .mu.m.sup.2 (.mu.m=micro meter).
The transistor T.sub.R as well presents problems in its fabrication, in view of its operating characteristics in relation to the conditions imposed by the RC precharging circuit, as illustrated in FIG. 1(a). Particularly, as the precharge voltage V.sub.n increase in amplitude, it imposes an increasing level of back bias voltage on transistor T.sub.R which functions to turn transistor T.sub.R OFF (i.e., render it nonconducting), prior to the precharging voltage V.sub.n increasing to the level of the high voltage source V.sub.pp, if transistor T.sub.R is an ordinary depletion (D) type transistor having an ordinary threshold voltage V.sub.th. Accordingly, conventional D type MIST devices cannot be used in a precharging circuit as shown in FIG. 1(a), since the precharging voltage V.sub.n cannot increase to the requisite level approaching V.sub.pp ; thus, the required long time interval as well cannot be achieved.
Accordingly, a modified transistor T.sub.R must be employed, known as a special D type MIST (or, also, as a modified MIST), which has a very low threshold voltage V.sub.th --meaning a threshold V.sub.th of a large absolute, but negative polarity, value. Such a modified MIST is very expensive, because its fabrication requires use of a special mask and ion implantation processes, for isolating it from other, conventional MIST's which may be adjacent to it in a memory chip. Particularly, the ion implantation is required for lowering the threshold voltage V.sub.th.
The use of a modified MIST, moreover, presents additional problems in view of the necessary relationship between channel width (W) and channel length (L). Particularly, as is well known, the current-voltage characteristic of a MIST (i.e., the characteristic relationship between the source-drain current and the gate-source voltage of the MIST) is such that the ratio of the source-drain current to the gate-source voltage is in proportion to the ratio W/L. Since the size (i.e., area on the chip) of a MIST depends mostly on the required channel length (L), to maintain a given current-voltage characteristic, factors affecting the channel width (W) correspondingly will affect the channel length (L) so as to maintain the required W/L ratio, and accordingly affect the required size of a MIST.
Thus, to minimize the size of the MIST, it is desirable to minimize the channel width (W)--i.e., to employ a narrow channel width (W). However, it is difficult to reduce the channel width (W) of a modified MIST to a value less than, or more narrow than, approximately 4 .mu.m. In general, this difficulty is presented in view of the necessary process steps performed in fabricating a MIST. Particularly, a channel cut is formed around the MIST by implanting boron ions (B.sup.+) around the field oxide layer (FOX) used as the source and the drain of the MIST, to avoid producing parasitic transistors in the chip. The boron ions thus implanted, however, tend to diffuse out beyond the channel cut and into surrounding portions of the chip, during thermal diffusion process steps.
The problems attendant fabrication of a modified MIST are more fully understood with reference to FIGS. 2(a) and 2(b), FIG. 2(a) comprising a cross-sectional view, in somewhat simplified schematic form, of such a modified MIST and FIG. 2(b) illustrating the corresponding threshold voltage V.sub.th characteristic, in relation to the configuration of the MIST and its channel width (W) as shown in FIG. 2(a). Particularly, the modified MIST 10 of FIG. 2(a) comprises a gate electrode 11, FOX layer 12, and boron doped regions 13 associated with the FOX layer 12. The channel width (W) of the MIST 10 schematically is illustrated to extend between the boundaries between the portions of the FOX 12 and the substrate underlying the gate electrode 11. The boron doped regions 13, however, overlap the peripheral portions of the channel width (W), which overlapped portions are designated .DELTA.W. The threshold voltage V.sub.th of modified MIST 10 is higher in the overlapped portions .DELTA.W of the channel width (W), than in the central or nonoverlapped portions (W-2 .DELTA.W). Stated alternatively, and with reference to the designations in FIG. 2(a), the combined overlapped portions (2 .DELTA.W) presents a high threshold voltage V.sub.th relative to the nonoverlapped portion (W-2.DELTA.W) having the desired, low threshold voltage V.sub.th. FIG. 2(b) illustrates the voltage threshold characteristic V.sub.th in relation to the channel width (W); as is readily seen therein, the threshold V.sub.th increases in the regions corresponding to the overlapped portions .DELTA.W.
Thus, since the size of the overlapped portions, 2 .DELTA.W, is a function of the required level of ion implantation represented by the boron doped regions 13, if the total width W is too narrow, the resulting threshold voltage V.sub.th is too high. Particularly, the portion 2 .DELTA.W having the high threshold voltage V.sub.th becomes superior to, or predominates, the central, nonoverlapped portion (W-2 .DELTA.W) having the low threshold voltage V.sub.th, out of the total channel width (W). Thus, it is difficult to fabricate a modified MIST which has a low threshold voltage V.sub.th, unless the channel width (W) is of substantial width.
For the reasons above explained, therefore, the channel width (W) of a modified MIST cannot be made narrow and as a result, to maintain a required ratio W/L to provide the requisite current-voltage characteristic, the channel length (L) as well must be large. Typically, the channel length (L) of a modified MIST must be in the range of from 100 .mu.m to 1,000 .mu.m, to achieve a time constant greater than 100 .mu.S for the RC precharging circuit. Thus, it has been impossible in the prior art to fabricate a capacitor C and a transistor T.sub.R which are small in size and yet satisfy the requirements of a precharging circuit as in FIG. 1(a) above discussed; in fact, it has been difficult to achieve a long time interval, such as 10 mS, even where a transistor T.sub.R has a channel length as great as 100 .mu.m and the capacitor C is of a size, or area, as great as 400.times.400 .mu.m.sup.2.
The channel length (L), moreover, presents yet another problem imposing practical limitations on successful implementation of the prior art circuits. Particularly, when the temperature of a memory chip increases, as is typical in normal operation, a leakage current which flows in a junction of the MIST correspondingly tends to increase. The leakage current must be compensated by causing a compensating current flow through the channel of the MIST. However, an adequate compensating current cannot be made to flow when the channel length (L) is as great as 1,000 .mu.m. As a result, to obtain the requisite long time interval, the only possibility is to increase the capacitance of capacitor C. However, increasing the capacitance imposes the necessary requirement of increasing the size of the capacitor C, and therefore the size of the memory chip.
Thus, precharging circuits of the prior art present serious problems in implementation, both as to cost and as to size; moreover, such prior art precharging circuits do not afford the high degree of reliability in operation which is desired.